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Out-of-order execution
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#	Item
21	Computer Science 246 Computer Architecture Spring 2013 Add to Reading List Source URL: www.eecs.harvard.edu Language: English - Date: 2013-02-28 10:17:41 Electronic engineering Register renaming Processor register Tomasulo algorithm Register file Instruction set Out-of-order execution Computer architecture Computer engineering Central processing unit
22	Hyper-Threading Technology Architecture and Microarchitecture Deborah T. Marr, Desktop Products Group, Intel Corp. Add to Reading List Source URL: users.ece.gatech.edu Language: English - Date: 2009-02-19 09:00:15 Central processing unit Threads Microprocessors Parallel computing Hyper-threading Simultaneous multithreading Multi-core processor Out-of-order execution CPU cache Computer architecture Computing Computer hardware
23	Non-deterministic Processors David May, Henk L. Muller, and Nigel P. Smart Department of Computer Science, Add to Reading List Source URL: saluc.engr.uconn.edu Language: English - Date: 2006-10-05 14:39:37 Parallel computing Central processing unit Superscalar Instruction register Microarchitecture Out-of-order execution Very long instruction word Instruction set Assembly language Computer architecture Computing Computer hardware
24	MICROPROCESSOR REPORT MIPS R10000 Uses Decoupled Architecture Add to Reading List Source URL: www.cs.cmu.edu Language: English - Date: 1997-10-06 18:42:23 R10000 MIPS architecture Out-of-order execution CPU cache Register renaming R4000 UltraSPARC Register file Reduced instruction set computing Computer hardware Computer architecture Computer engineering
25	PDF Document Add to Reading List Source URL: www.eecg.toronto.edu Language: English - Date: 2000-05-07 10:13:14 Classes of computers Instruction set architectures P6 Superscalar Pentium CPU cache P5 X86 Out-of-order execution Computer architecture Computing Computer engineering
26	PDF Document Add to Reading List Source URL: www.cs.ucsb.edu Language: English - Date: 1997-05-21 13:38:49 Central processing unit Classes of computers Object-oriented programming Parallel computing Superscalar CPU cache Thunk Branch predictor Out-of-order execution Computer architecture Computing Computer hardware
27	PDF Document Add to Reading List Source URL: electro.fisica.unlp.edu.ar Language: English - Date: 2006-10-27 10:47:00 Assembly languages Instruction set Addressing mode Out-of-order execution Instruction unit Instruction register Instruction pipeline Classic RISC pipeline X86 assembly language Computer architecture Instruction set architectures Central processing unit
28	PDF Document Add to Reading List Source URL: people.redhat.com Language: English - Date: 2009-02-04 10:36:05 Central processing unit X86 architecture Computer memory Classes of computers CPU cache P5 Pentium 4 X86 Out-of-order execution Computer architecture Computer hardware Computing

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